Field of the Invention
The invention relates to a clock buffer circuit, and, more particularly, to a power-mode-aware clock buffer circuit for an integrated circuit with multi-voltage design.
Description of the Related Art
In order to reduce power consumption, an integrated circuit with multi power modes is provided to provide different operation voltages for function modules. For example, the function module required to operate at full speed is provided with the maximum operation voltage. For an integrated circuit, the clock latency of one function module operating at one power mode is different from the clock latency of another function module operating at another power mode. Moreover, even though two function modules operate at the same power mode, the clock latency occurring in the two function modules is different due to characteristics of the element, the data transmission path, and so on. This difference in the clock latency may cause clock skew between the two function modules, which degrades system performance. Thus, a power-mode aware clock buffer circuit is required to eliminate clock skew.